A flash or block erase memory (flash memory), such as Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell, and thereby the memory as a whole, is made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash memory cell, includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. Programming occurs by hot electron injection in order to program the floating gate. Erasure employs Fowler-Nordheim tunneling effects in which electrons pass through a thin dielectric layer, thereby reducing the amount of charge on the floating gate. Erasing a cell sets the logical value of the cell to “1,” while programming a cell sets the logical value to “0.” The flash memory cell provides for nonvolatile data storage.
Prior Art FIG. 1 illustrates a typical configuration of a plan view of a section of a memory array 100 in a NOR-type of configuration for a memory device. Prior Art FIG. 1 is not drawn to scale. As shown in Prior Art FIG. 1, the array 100 is comprised of rows 110 and columns 120 of memory cells. Each of the memory cells are isolated from other memory cells by insulating layers, e.g., a plurality of shallow trench isolation regions (STI) 150.
A plurality of word lines 130 extend along the row direction. Bit lines extend in the column direction and are coupled to drain regions via drain contacts 160 in an associated column of memory cells 120. The bit lines are coupled to drain regions of memory cells in associated columns of memory cells 120.
A plurality of source lines 140 extend in the row direction and are coupled to the source regions of each of the memory cells in the array of memory cells 100. One source line is coupled to source regions in adjoining rows of memory cells, and as a result, one source region is shared between two memory cells. Similarly, drain regions are shared among adjoining rows of memory cells, and as a result, one drain region is shared between two memory cells.
Each of a plurality of source contacts 145 is coupled to the plurality of common source lines 140. Each of the plurality of source contacts 145 is formed in line with the associated common source line to which it is coupled. The source contacts are formed in a column 147, and may be connected with each other. The column 147 is isolated between two STI regions and forms a zone in which no memory cells are present.
As shown in FIG. 1, due to current photolithography limitations in forming contacts, each of the plurality of source contacts 145 is larger than their associated common source lines 140. As a result, the common source lines 140 need to be widened in the region surrounding their associated source contacts 145. This is to accommodate the wider source contacts 145. As such, word lines 130 on either side of the common source line 140 are bent to accommodate the increased area for the common source line surrounding an associated source contact 145.
Column 147 is wider than columns 120 in order to accommodate the bending of word lines 130 and is difficult to be scaled down. That is, as the size of each memory cell, and correspondingly the array 100 itself, is reduced, the bending of the word lines to accommodate the size of the source contacts is limited by current photolithography and other process techniques. For example, as the size shrinks, it becomes more difficult to form a pronounced bend in each of the plurality of word lines 130 at current pitches achievable by current photolithography techniques. As a result, the size of the overall array 100 is limited by the ability to bend the word lines 130.
Furthermore, the inability to form straight word lines in the region surrounding the source contacts 145 effects the uniformity of cells throughout the array 100. Specifically, the memory cells bordering the column 147 of source contacts that includes the source contacts 145 may have electrical characteristics (erase and program) that are different from those memory cells that do not border a column of source contacts. Core cell natural voltage and erased threshold voltage are specific problems.
A prior art example that attempts to address this problem is shown in Prior Art FIGS. 1B and 1C. Prior Art FIG. 1B is a planar view 100B of a section of a core memory array of memory cells in which a stripe 185 is implanted by implanting the source and drain sides of memory cells along a column that aligns with the source regions. On each side of the column an STI (shallow trench isolation) region 150 will have been formed. The source contacts 180 are formed on the wider drain side and the contacts 180 are connected to the Vss line 140 via implant stripe 185. Prior Art FIG. 1C is a cross-sectional view 100C of the core memory array of memory cells of FIG. 1B. Dotted line 150 represents the bottom of STI region (e.g., 150 in FIGS. 1A and 1B). FIG. 1C illustrates a problem that may exist with this approach. If the STI 150 is shallow and the implant layer 185 diffuses deep when contacts are formed, if the implant layer is misaligned, or if the bit line spacing is scaled down, then the dopant may diffuse laterally (as shown by section 165 diffusing below STI 150) through to bit lines (120B and/or 120C of FIG. 1B) and short out the adjacent transistor circuitry (bit-line “punch through”).